In digital communication systems, data is sent as a series of 1's and 0's. The voltage of an electrical signal is varied so that when a “1” is to be represented the signal has a first voltage, and when a “0” is to be represented the signal has a second voltage. The signal is transmitted by a transmitter and received by a receiver. In optical communication systems, the transmitter converts the electrical signal into an optical signal before transmission, and the receiver converts the optical signal back to an electrical signal. A Clock and Data Recovery module (CDR) recovers the 1's and 0's based on the voltages of the received electrical signal to produce a digital signal, and a Digital Wrapper module (DW) is used for error correction on the digital signal.
Both the optical signal and the electrical signal experience noise during transmission, and so the voltages of the electrical signal received by the CDR are clustered around both the first voltage and the second voltage. The CDR therefore employs a voltage threshold in determining whether the electrical signal is representing a “1” or a “0” at any particular sampling time. For example, if the first voltage (representing a “1”) is higher than the second voltage, then if the voltage of the electrical signal is above the threshold the CDR determines that the electrical signal is representing a “1”. If the electrical signal is below the threshold the CDR determines that the electrical signal is representing a “0”. If noise alters the voltage to the wrong side of the voltage threshold, a error occurs in reproducing the particular “1” or “0”. A Bit Error Rate (BER) is a measure of how many errors are occurring during reproduction of the 1's and 0's, i.e. during generation of the digital signal from the electrical signal.
Although it may appear that the voltage threshold should be set at the midpoint of the first voltage and the second voltage in order to minimize the BER, this is not necessarily the case. The level of noise may be dependent on the signal power, particularly in amplified systems or in systems employing Avalanche Photodiodes. If signal-dependent noise exists, then the higher of the first voltage and the second voltage will suffer more noise than the other. This results in an asymmetric eye diagram. See FIG. 1 for an illustration, in which the electrical signal suffers a Gaussian, signal-dependent noise distribution. If the voltage threshold is at the mid-point of the first voltage and the second voltage, then more errors will occur than if the voltage threshold is set lower. Of course some errors may be unavoidable if there is overlap between received voltages of 1's and of 0's, as shown in FIG. 1.
Communication systems therefore attempt to determine an optimum voltage threshold in order to improve receiver sensitivity. The optimum voltage threshold will vary from card to card depending on the type and quality of components on the card. Additionally, the optimum voltage threshold should also be dynamic for each card, so as to adapt to changing noise environment depending on the conditions under which each card is operated, or arising from ageing components or thermal drift.
In order to deal with changing noise environments and the resulting variable asymmetry in the eye diagram, the optimum voltage threshold is preferably determined intermittently. The optimum voltage threshold should also be determined intermittently in order to adjust for changing power levels in the optical portion of an optical communication system, since changing power levels will change the eye diagram if there is signal-dependent noise. One conventional way of doing this is to monitor FEC counters. ITU-T G.709 “Interface for the Optical Transport Network” provides, amongst other standards, a standard for forward error correction. Almost all G.709 compliant DW Application Specific Integrated Circuits (ASICs) generate FEC counters. The FEC counters are an indication of the raw BER before correction. The voltage threshold is adjusted by a voltage step, and the latest FEC counters read and used to estimate a new BER. This is repeated until the BER is minimized. However, a compromise must be made in selecting a voltage step size. The step size is a compromise between convergence time and precision of the optimum. Too small a step size will require many steps, and hence many seconds, to approach the optimum voltage threshold. Too large a step size will result in an imprecise optimum threshold.
Some optimum voltage threshold determination methods use CDR ASICs customized to a particular communication system. See for example U.S. Pat. No. 6,188,737 issued to Bruce et al. on Feb. 13, 2001. However, development of ASICs is costly, risky, and delays time-to-market. Additionally, the CDR ASIC taught by '737 has high power consumption due to duplication of the high-speed serial data path, and has difficulties optimizing the voltage threshold for high BERs. A method which uses widely available commercial CDR chips and FEC chips would be preferable, since no custom chips need to be designed.
In addition to the optimum voltage threshold, communication systems also need to determine an optimum phase sampling point. The optimum phase sampling point is the phase within the eye diagram at which the received voltages corresponding to 1's and the received voltages corresponding to 0's are furthest apart. This is the preferred sampling point for measuring the voltage in order to discriminate between 1's and 0's. If a phase sampling point other than the optimum phase sampling point is used, then the BER can increase as the transition region (between 1's and 0's) is approached. The optimum phase sampling point is coupled to the optimum voltage threshold, and a method of determining optimum parameters which takes advantage of this coupling is preferable to a method which determines each optimum parameter independently.